Super I/O
The Super I/O board is a feature of some Development Kits. The board is build around a SMSC LPC47M157 chip (Datasheet) and interfaces with the Xbox via a ribbon cable connected to the LPC Debug Port.
The board provides the following ports:
- RS232 (used for Kernel debugging, not to be confused with Xbox Debug Monitor)
unpopulated ports or functions are:
- PS/2 Mouse port[citation needed]
- PS/2 Keyboard port[citation needed]
- something MCPX (SMBus?)[citation needed]
- Temp something (SMBus?)[citation needed]
- Post code (SMBus?)[citation needed]
- Flash-ROM / BIOS (like modchips, replaces onboard kernel?)[citation needed]
Picture of the board[FIXME]
Schematic
Its a four layer board, layers 2 and 3 are filled on the entire board, probably ground and power planes. north, or up in the next tables is up as written the layer numbers and silkscreen common direction. The folowing main parts are populated on the board:
| total | Labels | Description |
|---|---|---|
| 1 | U1 | SMSC LPC47M157-NC (1996 ) |
| 0 | U2 | unpopulated DIP24 MCU(?) |
| 1 | U3 | MAX223EAI (0104, first week 2004?) |
| 1 | Y2 | CMX-309FB B (14.3181Mhz standard Clock Oscillator ) |
| 1 | J7 | AMP rs232 Male connector |
| 1 | J9 | 16 pins male header (LPC bus) |
| 5 | R1,R7,R10,R11,R12 | 10Kohm smd resistor |
| 7 | C10,C12,C13,C16,C17,C36,C37 | Bigger, probably NOT all the same caps |
| 17 | C1,C2,C9,C15,C1?(8?),C21,C22,C23,C24,C25,C26,C28,C31,C32,C33,C34,C35 | Smaller, also, asuming not all the same |
The connections in the following tables are checked with the continuity test on a VOM(Multimeter). but for now here are the listings of wich pin goes where:
U1 SMsC LPC ic
| Pin | to pin | Note |
|---|---|---|
| U1 pin 18 | C17(up) and ? | (not finished) |
| U1 pin 6,7 | C17(down) and GND | Both U1 pins yes) |
| U1 p24 | J9 pin 3 | LFrame |
| U1 p27 | R7 | Pull up (3.3v) |
| U1 p29 | J9 pin 1 | LClk |
| U1 p30 | J9 pin 16 | (unkown function) |
| U1 p40 | GND | |
| U1 p44 | 3.3v with C2 | Vcc? |
| U1 p45 | R1 (R2 unpopulated) | Pull down (R2 would be pullup 3.3v) |
| U1 p60 | GND | |
| U1 P84 | U3 P8, U2 P18 | RX |
| U1 P85 | U3 P6, U2 P17 | TX |
J9 LPC header
NOTE: version 1.3+ motherboards are missing the LFRAME signal which will need to be generated by an external CPLD [1]
NOTE: version 1.5 motherboards are missing pins 2 (GND) and 9 (VCC3), and pins 12 (GND) and 15 (VCC3) haven't been confirmed to work correctly[citation needed]
| Pin | Name | Type | Description | Termination(s) | Notes |
|---|---|---|---|---|---|
| 1 | LCLK | Output | PCI clock | U1 29 | |
| 2 | VSS | Power | System ground | (see
other parts) |
|
| 3 | LFRAME# | Output | Frame signal | U1 24 | Indicates start of a new cycle
and termination of broken cycle. |
| 4 | --- | --- | --- | --- | Voided to ensure correct ribbon
cable alignment. |
| 5 | LRST# | Output | PCI reset | U1 26 | Used as LPC interface reset. |
| 6 | VCC5 | Power | 5V power supply | (see
other parts) |
C12(e), C13(S), C15(S), U3 Pin
11 |
| 7 | LAD3 | I/O | LPC address/data bus | U1 23 | Multiplexed command, address and
data bus. |
| 8 | LAD2 | I/O | LPC address/data bus | U1 22 | Multiplexed command, address and
data bus. |
| 9 | VCC3 | Power | 3.3V power supply | (see
other parts) |
|
| 10 | LAD1 | I/O | LPC address/data bus | U1 21 | Multiplexed command, address and
data bus. |
| 11 | LAD0 | I/O | LPC address/data bus | U1 20 | Multiplexed command, address and
data bus. |
| 12 | VSS | Power | System ground | (see
other parts) |
|
| 13 | SCL | I/O | SMBus clock signal | U1 104 | |
| 14 | SDA | I/O | SMBus data signal | U1 103 | |
| 15 | VCC3 | Power | 3.3V power supply | (see
other parts) |
Intended to be used for external
IO board |
| 16 | L_SER_IRQ | Input | Serial interrupt requests | U1 30 | Provides a serial interrupt
request line for mouse/keyboard implementations of the IO board. |
Related links
(SMBus?)
