Difference between revisions of "DSP"
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Revision as of 20:13, 28 December 2018
The DSPs in the APU are probably "Parthus MediaStream" DSP cores (probably the 24-bit DSP2420 "Mozart" core).
Those are similar to Motorola DSP56362 (DSP56300 Family). If so, the datasheet can be found at http://www.nxp.com/docs/en/data-sheet/DSP56362.pdf (Also see "Documentation" section in said datasheet for the related documentation)
Memory Size
Program RAM Size | X Data RAM Size | Y Data RAM Size | MIXBUF Size | |
---|---|---|---|---|
GP | 4096 x 24-bit | 4096 x 24-bit | 2048 x 24-bit | 992[FIXME] x 24-bit |
EP | 4096 x 24-bit | 3072 x 24-bit | 256 x 24-bit | n/a |
MIXBUF is accessible at X:$001400 in the GP.
Other datasheets for similar DSPs suggest that the memory sizes might be different if instruction cache or switch mode are toggled. It is currently unknown if the DSPs in the Xbox APU support a similar feature[FIXME].
DMA
This section is very incomplete and not much was tested on hardware either
DMA is controlled using peripheral registers:
- 0xFFFFD4: Memory address of next command block
- 0xFFFFD5: DMA_START_BLOCK[FIXME]
- 0xFFFFD6: DMA_CONTROL[FIXME]
- 0xFFFFD7: DMA_CONFIGURATION[FIXME]
Additionally, bit 7 in the interrupt register at 0xFFFFC5 is set if a DMA End-Of-List has been encountered.
Command blocks
DSP command blocks are loaded from X-Memory.
Word | Meaning | Notes |
---|---|---|
0 | Next command block address | Memory address of next command block.
Bit 14 is used as End-Of-List marker. |
1 | Transfer control word | Controls the DMA transfer:
DSP address interleave (Bit-offset 0; 1-bit):
Direction (Bit-offset 1; 1-bit):
Unknown (Bit-offset 2; 2-bits):
Buffer offset writeback (Bit-offset 4; 1-bit): Only used for scratch buffers, behaves like 0 otherwise.[FIXME]
Buffer (Bit-offset 5; 4-bits):
Unknown (Bit-offset 9; 1-bit):
Sample format (Bit-offset 10; 3-bits): [FIXME]
Unknown (Bit-offset 13; 1-bit):
DSP address step size (Bit-offset 14; 10-bits): Used in DSP address calculation |
2 | Sample count | Behaviour depends on interleave setting
|
3 | DSP address | This is the address in the DSP:
|
4 | Buffer offset | Only used for scratch buffers, ignored otherwise.[FIXME]
This is the offset within the buffer where the first sample is accessed. If this is above or equal to the buffer end (buffer base + buffer size), then the write will behave like a non circular write. |
5 | Buffer base | Only used for circular buffers, ignored otherwise.[FIXME]
The start address of the buffer. |
6 | Buffer size | Only used for circular buffers, ignored otherwise.[FIXME]
Size of buffer minus 1. For a buffer with 0x1000 bytes, this has to be 0xFFF. |
FIFO
If the current address is below the base address when starting a transfer, it is moved to the base address. If the current address is above or equal to the end address when starting a transfer, the DSP hangs[FIXME].