Xyclops - Revision history

Prehistoricman: /* Internal registers */ Add reg 0xAA

2025-12-28T21:11:25Z

‎Internal registers: Add reg 0xAA

Prehistoricman at 18:18, 28 December 2025

2025-12-28T18:18:52Z

Prehistoricman: /* GPIO mapping */ Add GPIO pin numbers

2025-07-10T00:27:36Z

‎GPIO mapping: Add GPIO pin numbers

Prehistoricman: Add GPIO mapping table

2025-06-20T13:20:14Z

Add GPIO mapping table

Prehistoricman: Amending last edit

2025-06-20T12:46:09Z

Amending last edit

Prehistoricman: Add port registers

2025-06-20T01:03:11Z

Add port registers

Prehistoricman: Add some registers

2025-05-28T18:22:40Z

Add some registers

Prehistoricman: Update spare sector sizes

2025-05-28T14:57:06Z

Update spare sector sizes

Prehistoricman: Opcode 1E and 1F

2025-05-28T14:01:40Z

Opcode 1E and 1F

Prehistoricman at 13:01, 27 May 2025

2025-05-27T13:01:05Z

@@ Line 148: / Line 148: @@
 |-
 |A0||Port 2 output value (write) and input value (read)
 |-
 |B0||Port 0 tristate. 0 = output on. 1 = floating.

@@ Line 153: / Line 153: @@
 |C0||Port 1 tristate. 0 = output on. 1 = floating.
 |-
-|D7||SMBus related
+|D1||Fan PWM duty cycle or fan DAC level. 0xFF = fan off. 0 = fan full speed.
 |-
 |D8||Port 2 tristate. 0 = output on. 1 = floating.
@@ Line 162: / Line 168: @@
 |-
 |EC||Flash program/erase control. Bits 3:0 determine the flash region to target. Bits 7:5 control the kind of operation. Bit 4 starts the operation.
 |}

@@ Line 168: / Line 168: @@
 {| class="wikitable"
 |-
-!GPIO port.pin!!GPIO pin name!!Notes
+!GPIO port.pin!!Pin number!!GPIO pin name!!Notes
 |-
-|P0.0 || AUD_CLAMP ||
+|P0.0 || 59 || AUD_CLAMP ||
 |-
-|P0.1 || EJTSW ||
+|P0.1 || 7 ||  EJTSW ||
 |-
-|P0.2 || POWSW ||
+|P0.2 || 6 ||  POWSW ||
 |-
-|P0.3 || PSUON ||
+|P0.3 || 28 ||  PSUON ||
 |-
-|P0.4 || VREGON ||
+|P0.4 || 13 ||  VREGON ||
 |-
-|P0.5 || VPLLON ||
+|P0.5 || 26 ||  VPLLON ||
 |-
-|P0.6 || GPIO/FANOUT || FANOUT does not operate unless P0.6 is set high (regardless of open-drain/tri-state mode).
+|P0.6 || 32 ||  GPIO/FANOUT || FANOUT does not operate unless P0.6 is set high (regardless of open-drain/tri-state mode).
 |-
-|P0.7 || RTCACTIVE ||
+|P0.7 || 33 ||  RTCACTIVE ||
 |-
-|P1.0 || DVDEJECT ||
+|P1.0 || 5 ||  DVDEJECT ||
 |-
-|P1.1 || XCALRESET* ||
+|P1.1 || 40 ||  XCALRESET* ||
 |-
-|P1.2 || SCL ||
+|P1.2 || 35 ||  SCL ||
 |-
-|P1.3 || SDA ||
+|P1.3 || 34 ||  SDA ||
 |-
-|P1.4 || SMI* ||
+|P1.4 || 65 ||  SMI* ||
 |-
-|P1.5 || SYSRESET* ||
+|P1.5 || 41 ||  SYSRESET* ||
 |-
-|P1.6 || LEDGRN* ||
+|P1.6 || 11 ||  LEDGRN* ||
 |-
-|P1.7 || LEDRED* ||
+|P1.7 || 12 ||  LEDRED* ||
 |-
-|P2.0 || PSUGD ||
+|P2.0 || 14 ||  PSUGD ||
 |-
-|P2.1 || VREGGD ||
+|P2.1 || 27 ||  VREGGD ||
 |-
-|P2.2 || VMODE<0> ||
+|P2.2 || 42 ||  VMODE<0> ||
 |-
-|P2.3 || VMODE<1> ||
+|P2.3 || 43 ||  VMODE<1> ||
 |-
-|P2.4 || VMODE<2> ||
+|P2.4 || 44 ||  VMODE<2> ||
 |-
-|P2.5 || TRAYSTATE<0> ||
+|P2.5 || 62 ||  TRAYSTATE<0> ||
 |-
-|P2.6 || TRAYSTATE<1> ||
+|P2.6 || 61 ||  TRAYSTATE<1> ||
 |-
-|P2.7 || TRAYSTATE<2> ||
+|P2.7 || 60 ||  TRAYSTATE<2> ||
 |}

@@ Line 162: / Line 162: @@
 |-
 |EC||Flash program/erase control. Bits 3:0 determine the flash region to target. Bits 7:5 control the kind of operation. Bit 4 starts the operation.
 |}

@@ Line 156: / Line 156: @@
 |-
 |D8||Port 2 tristate. 0 = output on. 1 = floating.
 |-
 |D9 - DE||SMBus related

@@ Line 134: / Line 134: @@
 |-
 !Address (hex)!!Purpose
 |-
 |91||BIOS flash bank select. 0 - 3 for 256KiB.
 |-
 |D7||SMBus related
 |-
 |D8||GPIO port 2 related (seemingly related to reading pin states)

@@ Line 136: / Line 136: @@
 |-
 |91||BIOS flash bank select. 0 - 3 for 256KiB.
 |-
 |E9||Debug serial baud control. Higher value = faster serial. 0xB0 = 9600. 0xEC = 38400 baud
 |}

@@ Line 60: / Line 60: @@
 |18 and 19||4||2||Read 1 byte from spare sector 0 or 1
 |-
-|1A and 1B||4||2||Program 1 byte of spare sector 0 or 1. Needs to be unlocked by opcode 0x43. Addresses are aliased within the 1KiB or 0.5KiB flash space.
+|1A and 1B||4||2||Program 1 byte of spare sector 0 or 1. Needs to be unlocked by opcode 0x43. Addresses are aliased within the 2KiB or 0.5KiB memory space.
 |-
 |1C and 1D||4||65||Read 64 bytes from spare sector 0 or 1
@@ Line 108: / Line 108: @@
 |85||4||2||Mass erase SMC flash. Takes about 350ms.
 |-
-|88||4||2||Erase spare sector 0 (0x400 bytes)
+|88||4||2||Erase spare sector 0 (0x200 bytes)
 |-
-|89||4||2||Erase spare sector 1 (0x200 bytes)
+|89||4||2||Erase spare sector 1 (0x80 bytes)
 |-
 |8C||4||2||Erase spare sector 0
@@ Line 125: / Line 125: @@
 * 256KiB BIOS flash (4 banks)
 ** Bank selected by register 0x91
-* 1KiB spare sector 0
+* 512-byte spare sector 0
-* 0.5KiB spare sector 1
+* 128-byte spare sector 1
 * 256-byte mixed RAM+SFR space (first 128 is RAM, second 128 is SFRs)

@@ Line 64: / Line 64: @@
 |1C and 1D||4||65||Read 64 bytes from spare sector 0 or 1
 |-
-|1E and 1F||?||?||Assumed to be program 64 bytes of spare sector 0 or 1
+|1E and 1F||67||2||Program 64 bytes of spare sector 0 or 1
 |-
 |20 and 21||4||2||Read 1 byte of RAM/SFRs

@@ Line 122: / Line 122: @@
 ** Upper 128 bytes read out as semi-random values. The 8051 core would need a bank select to naturally access them.
 * 16KiB SMC flash
-* 1KiB debug ROM (at address 0xFC00 in the SMC flash space)
+* 1KiB SMC debug ROM (at address 0xFC00 in the SMC flash space)
 * 256KiB BIOS flash (4 banks)
 ** Bank selected by register 0x91