Super I/O - Revision history

Codeasm: Finnaly added that image, a Super I/O board from a DVT4

2021-06-26T22:25:05Z

Finnaly added that image, a Super I/O board from a DVT4

Ernegien: /* Schematic */

2018-02-13T07:43:07Z

‎Schematic

Ernegien: /* U1 SMsC LPC ic */

2018-02-13T07:26:50Z

‎U1 SMsC LPC ic

Show changes

Ernegien: /* Related links */

2018-02-13T06:30:40Z

‎Related links

Ernegien: /* J9 LPC header */

2018-02-13T06:25:07Z

‎J9 LPC header

Ernegien: /* J9 LPC header */

2018-02-13T06:22:45Z

‎J9 LPC header

Codeasm: Added U2 detail, not much, only serial pins

2018-02-06T20:22:42Z

Added U2 detail, not much, only serial pins

Codeasm: /* U1 SMsC LPC ic */ updates for pins 27,40, 44,45 and 60 (pins RX and TX on MAX223)

2018-02-06T20:11:57Z

‎U1 SMsC LPC ic: updates for pins 27,40, 44,45 and 60 (pins RX and TX on MAX223)

Furon at 20:56, 30 December 2017

2017-12-30T20:56:35Z

Codeasm: /* Schematic */ done for today. will continue soon

2017-08-17T21:13:40Z

‎Schematic: done for today. will continue soon

@@ Line 1: / Line 1: @@
 The Super I/O board is a feature of some [[Development Kits]]. The board is build around a SMSC LPC47M157 chip ([https://drive.google.com/uc?export=download&id=0BxOesalXbGtOanoxenlqQUh6Y0k Datasheet]) and interfaces with the Xbox via a ribbon cable connected to the [[LPC Debug Port]].
 The board provides the following ports:
@@ Line 11: / Line 13: @@
 * Post code (SMBus?){{citation needed}}
 * Flash-ROM / BIOS (like modchips, replaces onboard kernel?){{citation needed}}
 == Schematic ==

@@ Line 249: / Line 249: @@
 * [https://github.com/espes/xqemu/blob/xbox/hw/xbox/lpc47m157.c Super I/O emulation in XQEMU]
 (SMBus?)
-* [http://imgur.com/a/vJi9E Images (CC0 License) by Codeasm with detailed shots of the SuperIO board]
+* [https://imgur.com/a/ROMYa Images (CC0 License) by Codeasm with detailed shots of the SuperIO board]

@@ Line 143: / Line 143: @@
 | Power
 | System ground
-| (see
+| (see other parts)
+|
 |-
@@ Line 152: / Line 151: @@
 | Frame signal
 | U1 24
-| Indicates start of a new cycle
+| Indicates start of a new cycle and termination of broken cycle.
 |-
 | 4
@@ Line 160: / Line 158: @@
 | ---
 | ---
-| Voided to ensure correct ribbon
+| Voided to ensure correct ribbon cable alignment.
 |-
 | 5
@@ Line 174: / Line 171: @@
 | Power
 | 5V power supply
-| (see
+| (see other parts)
-other parts)
+| C12(e), C13(S), C15(S), U3 11
 |-
 | 7
@@ Line 184: / Line 179: @@
 | LPC address/data bus
 | U1 23
-| Multiplexed command, address and
+| Multiplexed command, address and data bus.
 |-
 | 8
@@ Line 192: / Line 186: @@
 | LPC address/data bus
 | U1 22
-| Multiplexed command, address and
+| Multiplexed command, address and data bus.
 |-
 | 9
@@ Line 199: / Line 192: @@
 | Power
 | 3.3V power supply
-| (see
+| (see other parts)
+|
 |-
@@ Line 208: / Line 200: @@
 | LPC address/data bus
 | U1 21
-| Multiplexed command, address and
+| Multiplexed command, address and data bus.
 |-
 | 11
@@ Line 216: / Line 207: @@
 | LPC address/data bus
 | U1 20
-| Multiplexed command, address and
+| Multiplexed command, address and data bus.
 |-
 | 12
@@ Line 223: / Line 213: @@
 | Power
 | System ground
-| (see
+| (see other parts)
+|
 |-
@@ Line 245: / Line 234: @@
 | Power
 | 3.3V power supply
-| (see
+| (see other parts)
-other parts)
+| Intended to be used for external IO board
 |-
 | 16
@@ Line 255: / Line 242: @@
 | Serial interrupt requests
 | U1 30
-| Provides a serial interrupt
+| Provides a serial interrupt request line for mouse/keyboard implementations of the IO board.
 |}

@@ Line 119: / Line 119: @@
 === J9 LPC header===
-Not finished
 {| class="wikitable"
 !| Pin
-! to pin
+! Name
-! Note
+! Type
 |-
-|J9 pin 1
+| 1
-|U1 p29
+| LCLK
+| Output
 |-
-|J9 pin 2
+| 2
-|GND
+| VSS
+| Power
 |-
-|J9 pin 3
+| 3
-|U1 p24
+| LFRAME#
-|LFrame
+| Output
 |-
-|J9 pin 4
+| 4
-|NC
+| ---
-|no pin
+| ---
 |-
-|J9 pin 5
+| 5
+| LRST#
-|RST
+| Output
 |-
-|J9 pin 6
+| 6
-|C12(e),C13(S),C15(S),U3 p11.
+| VCC5
-|5V
+| Power
 |-
-|J9 pin 7
+| 7
+| LAD3
-|LAD3
+| I/O
 |-
-|J9 pin 8
+| 8
+| LAD2
-|LAD2
+| I/O
 |-
-|J9 pin 9
+| 9
-|3.3V
+| VCC3
+| Power
 |-
-|J9 pin 10
+| 10
+| LAD1
-|LAD1
+| I/O
 |-
-|J9 pin 11
+| 11
+| LAD0
-|LAD0
+| I/O
 |-
-|J9 pin 12
+| 12
-|GND
+| VSS
+| Power
 |-
-|J9 pin 13
+| 13
-|U1 p104
+| SCL
-|SCL
+| I/O
 |-
-|J9 pin 14
+| 14
-|U1 p103
+| SDA
-|SDA
+| I/O
 |-
-|J9 pin 15
+| 15
-|3.3V
+| VCC3
+| Power
 |-
-|J9 pin 16
+| 16
-|U1 p30
+| L_SER_IRQ
-|(unkown function)
+| Input
 |}

@@ Line 26: / Line 26: @@
 | U1
 | SMSC LPC47M157-NC (1996 )
 |-
 |1
@@ Line 106: / Line 110: @@
 |-
 |U1 P84
-|U3 P8
+|U3 P8, U2 P18
 |RX
 |-
 |U1 P85
-|U3 P6
+|U3 P6, U2 P17
 |TX
 |}

@@ Line 62: / Line 62: @@
 The connections in the following tables are checked with the continuity test on a VOM(Multimeter).
 but for now here are the listings of wich pin goes where:
 === U1 SMsC LPC ic ===

← Older revision		Revision as of 20:56, 30 December 2017
Line 1:		Line 1:
−	The Super I/O board is a feature of [[Development Kits]]. The board is build around a SMSC LPC47M157 chip ([https://drive.google.com/uc?export=download&id=0BxOesalXbGtOanoxenlqQUh6Y0k Datasheet])	+	The Super I/O board is a feature of some [[Development Kits]]. The board is build around a SMSC LPC47M157 chip ([https://drive.google.com/uc?export=download&id=0BxOesalXbGtOanoxenlqQUh6Y0k Datasheet]) and interfaces with the Xbox via a ribbon cable connected to the [[LPC Debug Port]].

	The board provides the following ports:		The board provides the following ports:

@@ Line 15: / Line 15: @@
 == Schematic ==
-Its a four layer board, layers 2 and 3 are filled on the entire board, probablu ground and power planes.
+Its a four layer board, layers 2 and 3 are filled on the entire board, probably ground and power planes.
 north, or up in the next tables is up as written the layer numbers and silkscreen common direction.
 The folowing main parts are populated on the board:
@@ Line 55: / Line 55: @@
 |Smaller, also, asuming not all the same
 |}
 {| class="wikitable"
 !| Pin
@@ Line 70: / Line 73: @@
 |Both U1 pins yes)
 |-
+|U1 p24
 |}
+=== J9 LPC header===
 {| class="wikitable"
 !| Pin
@@ Line 80: / Line 102: @@
 |-
 |J9 pin 1
+|
 |-
 |J9 pin 2
@@ Line 88: / Line 110: @@
 |-
 |J9 pin 3
+|U1 p24
-|(not finished)
+|LFrame
 |-
 |J9 pin 4
@@ Line 97: / Line 119: @@
 |J9 pin 5
+|
-|RST(not finished)
+|RST
 |-
 |J9 pin 6
 |C12(e),C13(S),C15(S),U3 p11.
-|5V(not finished)
+|5V
 |-
 |J9 pin 7
+|
-|LAD3(not finished)
+|LAD3
 |-
 |J9 pin 8
+|
-|LAD2(not finished)
+|LAD2
 |-
 |J9 pin 9
 |3.3V
-|(not finished)
 |-
 |J9 pin 10
+|
-|LAD1(not finished)
+|LAD1
 |-
 |J9 pin 11
+|
-|LAD0(not finished)
+|LAD0
 |-
 |J9 pin 12
@@ Line 128: / Line 150: @@
 |-
 |J9 pin 13
+|U1 p104
-|SCL(not finished)
+|SCL
 |-
 |J9 pin 14
+|U1 p103
-|SDA(not finished)
+|SDA
 |-
 |J9 pin 15
 |3.3V
-|(not finished)
 |-
 |J9 pin 16
+|U1 p30
-|(not finished)
+|(unkown function)
 |}